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FEATURES
POWER MANAGER n High Efficiency Switching PowerPathTM Controller with Bat-TrackTM Adaptive Output Control n Programmable USB or Wall Current Limit (100mA/500mA/1A) n Full Featured Li-Ion/Polymer Battery Charger n Instant-On Operation with a Discharged Battery n 1.5A Maximum Charge Current n Internal 180m Ideal Diode Plus External Ideal Diode Controller Powers Load in Battery Mode n Low No-Load I when Powered from BAT (<30A) Q DC/DCs n Dual High Efficiency Buck DC/DCs (400mA/400mA I OUT) n High Efficiency Buck-Boost DC/DC (1A I ) OUT n All Regulators Operate at 2.25MHz n Dynamic Voltage Scaling on Two Buck Outputs n I2C Control of Enables, Mode, Two V OUT Settings n ENALL Pin with Power-Up Sequence Control n Low No-Load Quiescent Current: 20A Each
LTC3556 High Efficiency USB Power Manager with Dual Buck and Buck-Boost DC/DCs DESCRIPTION
The LTC(R)3556 is a highly integrated power management and battery charger IC for Li-Ion/Polymer battery applications. It includes a high efficiency current limited switching PowerPath manager with automatic load prioritization, a battery charger, an ideal diode, and three synchronous switching regulators (two bucks and one buck-boost). Designed specifically for USB applications, the LTC3556's switching power manager automatically limits input current to a maximum of either 100mA or 500mA for USB applications or 1A for adapter-powered applications. The LTC3556's switching input stage transmits nearly all of the 2.5W available from the USB port to the system load with minimal power wasted as heat. This feature allows the LTC3556 to provide more power to the application and eases the constraint of thermal budgeting in small spaces. The two buck regulators can provide up to 400mA each and the buck-boost can deliver 1A. The LTC3556 is available in the low profile 28-pin (4mm x 5mm x 0.75mm) QFN surface mount package.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. PowerPath and Bat-Track are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 6522118 and 6404251.
APPLICATIONS
n n
HDD-Based MP3 Players, PDAs, GPS, PMPs Other USB-Based Handheld Products
TYPICAL APPLICATION
High Efficiency PowerPath Manager, Dual Buck, Buck-Boost and LDO
USB/WALL 4.5V TO 5.5V USB COMPLIANT STEP-DOWN REGULATOR CC/CV BATTERY CHARGER CHARGE T LTC3556 ALWAYS ON LDO ENALL SEQ I2C 3 DUAL HIGH EFFICIENCY BUCKS HIGH EFFICIENCY BUCK-BOOST I2C PORT 1 2 3 3.3V/25mA 0.8V TO 3.6V/400mA 0.8V TO 3.6V/400mA RTC/LOW POWER LOGIC MEMORY CORE P 0V OPTIONAL TO OTHER LOADS 700 600 CHARGE CURRENT (mA) 500 400 300 200 100 0 2.8 3 VBUS = 5V 5X MODE BATTERY CHARGER PROGRAMMED FOR 1A 3.2 3.4 3.6 3.8 BATTERY VOLTAGE (V) 4 4.2
Battery Charge Current vs Battery Voltage
BATTERY CHARGE CURRENT EXTRA CURRENT FOR FASTER CHARGING 500mA USB CURRENT LIMIT
+
Li-Ion
2.5V to 3.3V/1A PGOODALL
HDD/IO
3556 TA01
3556 TA01b
3556f
1
LTC3556 ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
ENALL TOP VIEW VBUS VOUT SCL SEQ BAT 22 GATE 21 CHRG 20 PROG 29 19 SW2 18 VIN2 17 FB2 16 SDA 15 PGOODALL 9 10 11 12 13 14 SWAB3 DVCC VIN3 SWCD3 VOUT3 SW
VBUS (Transient) t < 1ms, Duty Cycle < 1% .. -0.3V to 7V VIN1, VIN2, VIN3, VBUS (Static), DVCC, FB1, FB2, NTC, BAT, ENALL, SCL, SDA, PGOODALL, CHRG ....................................... -0.3V to 6V SEQ ....................-0.3V to Lesser of 6V or (VOUT + 0.3V) FB3, VC3 .............. -0.3V to Lesser of 6V or (VIN3 + 0.3V) ICLPROG ....................................................................3mA IPGOODALL, ICHRG ....................................................50mA IPROG ........................................................................2mA ILDO3V3 ...................................................................30mA ISW1, ISW2 ............................................................600mA ISW, IBAT, IVOUT.............................................................2A ISWAB3, ISWCD3, IVOUT3 .............................................2.5A Operating Temperature Range (Note 2).... -40C to 85C Junction Temperature (Note 3) ............................. 125C Storage Temperature Range................... -65C to 125C
28 27 26 25 24 23 LDO3V3 1 CLPROG 2 NTC 3 SW1 4 VIN1 5 FB1 6 FB3 7 VC3 8
UFD PACKAGE 28-LEAD (4mm 5mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC3556EUFD#PBF TAPE AND REEL LTC3556EUFD#TRPBF PART MARKING 3556 PACKAGE DESCRIPTION 28-Lead (4mm x 5mm) Plastic QFN TEMPERATURE RANGE -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
SYMBOL VBUS IBUSLIM PARAMETER Input Supply Voltage Total Input Current PowerPath Switching Regulator
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
CONDITIONS MIN 4.35 1x Mode, VOUT = BAT 5x Mode, VOUT = BAT 10x Mode, VOUT = BAT Suspend Mode, VOUT = BAT 1x Mode, IOUT = 0mA 5x Mode, IOUT = 0mA 10x Mode, IOUT = 0mA Suspend Mode, IOUT = 0mA 1x Mode 5x Mode 10x Mode Suspend Mode
l l l l
TYP
MAX 5.5
UNITS V mA mA mA mA mA mA mA mA mA/mA mA/mA mA/mA mA/mA
3556f
87 436 800 0.31
95 460 860 0.38 7 15 15 0.044 224 1133 2140 11.3
100 500 1000 0.50
IVBUSQ
VBUS Quiescent Current
hCLPROG (Note 4)
Ratio of Measured VBUS Current to CLPROG Program Current
2
LTC3556 ELECTRICAL CHARACTERISTICS
SYMBOL IOUT(POWERPATH) PARAMETER
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
CONDITIONS MIN TYP 135 672 1251 0.32 1.188 100 3.95 4.30 4.00 200 50 3.4 4.5
l
MAX
UNITS mA mA mA mA V mV
VOUT Current Available Before Loading 1x Mode, BAT = 3.3V BAT 5x Mode, BAT = 3.3V 10x Mode, BAT = 3.3V Suspend Mode CLPROG Servo Voltage in Current Limit VBUS Undervoltage Lockout VBUS to BAT Differential Undervoltage Lockout VOUT Voltage 1x, 5x, 10x Modes Suspend Mode Rising Threshold Falling Threshold Rising Threshold Falling Threshold 1x, 5x, 10x Modes, 0V < BAT < 4.2V, IOUT = 0mA, Battery Charger Off USB Suspend Mode, IOUT = 250A
VCLPROG VUVLO_VBUS VUVLO_VBUS-BAT VOUT
4.35
V V mV mV
BAT + 0.3 4.6 2.25 0.18 0.30
4.7 4.7 2.7
V V MHz A A
fOSC
Switching Frequency
1.8
RPMOS_POWERPATH PMOS On-Resistance RNMOS_POWERPATH NMOS On-Resistance IPEAK_POWERPATH Battery Charger VFLOAT ICHG IBAT VPROG VPROG_TRKL VC/10 hPROG ITRKL VTRKL VTRKL VRECHRG tTERM tBADBAT hC/10 VCHRG ICHRG RON_CHG TLIM BAT Regulated Output Voltage Constant Current Mode Charge Current Battery Drain Current PROG Pin Servo Voltage PROG Pin Servo Voltage in Trickle Charge C/10 Threshold Voltage at PROG Ratio of IBAT to PROG Pin Current Trickle Charge Current Trickle Charge Threshold Voltage Trickle Charge Hysteresis Voltage Recharge Battery Threshold Voltage Safety Timer Termination Bad Battery Termination Time CHRG Pin Output Low Voltage CHRG Pin Leakage Current Battery Charger Power FET On-Resistance (Between VOUT and BAT) Junction Temperature in Constant Temperature Mode Threshold Voltage Relative to VFLOAT Timer Starts When BAT = VFLOAT BAT < VTRKL ICHRG = 5mA VCHRG = 5V -75 3.3 0.42 0.088 BAT < VTRKL BAT Rising 2.7 BAT < VTRKL
l
Peak Switch Current Limit
1x, 5x Modes 10x Mode 4.179 4.165 980 185 2
2 3 4.200 4.200 1022 204 3.5 27 1.000 0.100 100 1022 100 2.85 135 -100 4 0.5 0.1 65 0.18 110 -125 5 0.63 0.112 100 1 3.0 4.221 4.235 1065 223 5 38
V V mA mA A A V V mV mA/mA mA V mV mV Hour Hour mA/mA mV A C
RPROG = 5k VBUS > VUVLO, Battery Charger Off, IOUT = 0A VBUS = 0V, IOUT = 0A (Ideal Diode Mode)
End of Charge Indication Current Ratio (Note 5)
3556f
3
LTC3556 ELECTRICAL CHARACTERISTICS
SYMBOL NTC VCOLD VHOT VDIS INTC Ideal Diode VFWD RDROPOUT IMAX_DIODE VLDO3V3 RCL_LDO3V3 ROL_LDO3V3 VIL VIH RPD VOL IOH tPGOODALL I2C Port (Note 9) DVCC IDVCC VDVCC_UVLO ADDRESS VIH SDA, SCL VIL SDA, SCL IIH, IIL SDA, SCL VOL SDA fSCL tBUF tHD_STA tSU_STA tSU_STO tHD_DAT(O) Input Supply Voltage DVCC Current DVCC UVLO I2C Address Input High Voltage Input Low Voltage Input High/Low Current SDA Output Low Voltage Clock Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Output 1.3 0.6 0.6 0.6 0 900 ISDA = 3mA 70 30 -1 0 1 0.4 400 SCL/SDA = 0kHz 1.6 0.3 1.0 0001 001[0] %DVCC %DVCC A V kHz s s s s ns
3556f
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
PARAMETER Cold Temperature Fault Threshold Voltage Hot Temperature Fault Threshold Voltage NTC Disable Threshold Voltage NTC Leakage Current Forward Voltage CONDITIONS Rising Threshold Hysteresis Falling Threshold Hysteresis Falling Threshold Hysteresis VNTC = VBUS = 5V VBUS = 0V, IOUT = 10mA IOUT = 10mA 1.6 0mA < ILDO3V3 < 25mA 3.1 3.3 4 23 ENALL Pin ENALL Pin ENALL Pin PGOODALL Pin, IPULL-UP = 5mA PGOODALL Pin, VPGOODALL = 5V 230 5.5 1 1.2 4.5 0.07 0.2 1 0.4 3.5 MIN 75.0 33.4 0.7 -50 2 15 0.18 TYP 76.5 1.5 34.9 1.5 1.7 50 MAX 78.0 36.4 2.7 50 UNITS %VBUS %VBUS %VBUS %VBUS %VBUS mV nA mV mV A V V V M V A ms V A V
Internal Diode On-Resistance, Dropout VBUS = 0V Internal Diode Current Limit Regulated Output Voltage Closed-Loop Output Resistance Dropout Output Resistance Logic Low Input Voltage Logic High Input Voltage Pull-Down Resistance Logic Low Output Voltage Logic High Leakage Current PGOODALL Assertion Delay
Always On 3.3V Supply
Logic (ENALL, PGOODALL)
4
LTC3556 ELECTRICAL CHARACTERISTICS
SYMBOL tHD_DAT(I) tSU_DAT tLOW tHIGH tf tr tSP VIN1,2,3 VOUTUVLO PARAMETER Data Hold Time Input Data Setup Time SCL Clock Low Period SCL Clock High Period Clock/Data Fall Time Clock/Data Rise Time Input Spike Suppression Pulse Width Input Supply Voltage VOUT UVLO--VOUT Falling VOUT UVLO--VOUT Rising Oscillator Frequency Pulse Skip Mode Input Current Burst Mode(R) Input Current Forced Burst Mode Input Current LDO Mode Input Current Shutdown Input Current PMOS Switch Current Limit Available Output Current IOUT1 = 0A (Note 6) IOUT1 = 0A (Note 6) IOUT1 = 0A (Note 6) IOUT1 = 0A (Note 6) IOUT1 = 0A, FB1 = 0V Pulse Skip/Burst Mode Operation Pulse Skip/Burst Mode Operation (Note 9) Forced Burst Mode Operation (Note 9) LDO Mode (Note 9) Full Scale (1, 1, 1, 1) (Note 7) Zero Scale (0, 0, 0, 0) (Note 7)
l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
CONDITIONS MIN 0 100 1.3 0.6 CB = Capacitance of One BUS Line (pF) CB = Capacitance of One BUS Line (pF) 20 + 0.1CB 20 + 0.1CB 300 300 50 2.7 VIN1,2,3 Connected to VOUT Through Low Impedance. Switching Regulators are Disabled in UVLO
l
TYP
MAX
UNITS ns ns s s ns ns ns V V V MHz A A A A A mA mA mA mA
Switching Regulators 1, 2 and 3 5.5 2.6 2.8 2.25 225 35 20 20 600 400 60 50 0.780 0.405 0.800 0.425 25 0.6 0.7 0.25 (Note 8) VFB1 = 0.85V
l
2.5
2.9 2.7 400 60 35 35 1 1100
fOSC IVIN1
1.8
Switching Regulator 1 (Buck)
ILIM1 IOUT1
800
VFBHIGH1 VFBLOW1 VLSB1 RP1 RN1 RLDO_CL1 RLDO_OL1 IFB1 D1 RSW1 IVIN2
Maximum Servo Voltage Minimum Servo Voltage VFB1 Servo Voltage Step Size PMOS RDS(ON) NMOS RDS(ON) LDO Mode Closed-Loop ROUT LDO Mode Open-Loop ROUT FB1 Input Current Maximum Duty Cycle SW1 Pull-Down in Shutdown Pulse Skip Mode Input Current Burst Mode Input Current Forced Burst Mode Input Current LDO Mode Input Current Shutdown Input Current PMOS Switch Current Limit Available Output Current
0.820 0.445
V V mV
2.5 -50 100 10 50
nA % k
Switching Regulator 2 (Buck) IOUT2 = 0A (Note 6) IOUT2 = 0A (Note 6) IOUT2 = 0A (Note 6) IOUT2 = 0A (Note 6) IOUT2 = 0A, FB2 = 0V Pulse Skip/Burst Mode Operation Pulse Skip/Burst Mode Operation (Note 9) Forced Burst Mode Operation (Note 9) LDO Mode (Note 9) 600 400 60 50 225 35 20 20 800 400 60 35 35 1 1100 A A A A A mA mA mA mA
3556f
ILIM2 IOUT2
Burst Mode is a registered trademark of Linear Technology Corporation.
5
LTC3556 ELECTRICAL CHARACTERISTICS
SYMBOL VFB2 RP2 RN2 RLDO_CL2 RLDO_OL2 IFB2 D2 RSW2 IVIN3 PARAMETER VFB2 Servo Voltage PMOS RDS(ON) NMOS RDS(ON) LDO Mode Closed-Loop ROUT LDO Mode Open-Loop ROUT FB2 Input Current Maximum Duty Cycle SW2 Pull-Down in Shutdown Input Current PWM Mode, IOUT3 = 0A Burst Mode Operation, IOUT3 = 0A Shutdown For Burst Mode Operation or Synchronous PWM Operation 5.50 PWM Mode
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBUS = 5V, VIN1 = VIN2 = VIN3 = VOUT3 = 3.8V, BAT = 3.8V, DVCC = 3.3V, RPROG = 1k, RCLPROG = 3.01k, unless otherwise noted.
CONDITIONS (Note 7)
l
MIN 0.780
TYP 0.800 0.6 0.7 0.25
MAX 0.820
UNITS V
(Note 8) VFB2 = 0.85V
l
2.5 -50 100 10 220 13 0 2.65 5.60 2.5 275 0 3 350 30 400 20 1 2.75 50
nA % k A A A V V A mA mA mA
Switching Regulator 3 (Buck-Boost)
VOUT3(LOW) VOUT3(HIGH) ILIMF3 IPEAK3(BURST) IZERO3(BURST) IMAX3(BURST) VFBHIGH3 VFBLOW3 VLSB3 IFB3 RDS(ON)P RDS(ON)N ILEAK(P) ILEAK(N) RVOUT3 DBUCK(MAX) DBOOST(MAX) tSS3
Minimum Regulated Output Voltage Maximum Regulated Output Voltage Forward Current Limit (Switch A)
2 200 -30 50
Forward Burst Current Limit (Switch A) Burst Mode Operation Reverse Burst Current Limit (Switch D) Burst Mode Operation Maximum Deliverable Output Current in Burst Mode Operation Maximum Servo Voltage Minimum Servo Voltage VFB3 Servo Voltage Step Size FB3 Input Current PMOS RDS(ON) NMOS RDS(ON) PMOS Switch Leakage NMOS Switch Leakage VOUT3 Pull-Down in Shutdown Maximum Buck Duty Cycle Maximum Boost Duty Cycle Soft-Start Time PWM Mode PWM Mode VFB3 = 0.8V Switches A, D Switches B, C Switches A, D Switches B, C 2.7V VIN3 5.5V, 2.75V VOUT3 5.5V (Note 9) Full Scale (1, 1, 1, 1) Zero Scale (0, 0, 0, 0)
l l
0.780 0.405 -50
0.800 0.425 25
0.820 0.445 50
V V mV nA
0.22 0.17 -1 -1 10
l
1 1
A A k % % ms
100 75 0.5
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3556E is guaranteed to meet performance specifications from 0C to 85C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: The LTC3556E includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
Note 4: Total input current is the sum of quiescent current, IVBUSQ, and measured current given by: VCLPROG/RCLPROG * (hCLPROG +1) Note 5: hC/10 is expressed as a fraction of measured full charge current with indicated PROG resistor. Note 6: FBx above regulation such that regulator is in sleep. Specification does not include resistive divider current reflected back to VINx. Note 7: Applies to Pulse Skip, Burst Mode operation and Forced Burst Mode operation only. Note 8: Inductor series resistance adds to open-loop ROUT. Note 9: Guaranteed by design.
3556f
6
LTC3556 TYPICAL PERFORMANCE CHARACTERISTICS
Ideal Diode V-I Characteristics
1.0 INTERNAL IDEAL DIODE WITH SUPPLEMENTAL EXTERNAL VISHAY Si2333 PMOS RESISTANCE () 0.25
Ideal Diode Resistance vs Battery Voltage
4.50
Output Voltage vs Load Current (Battery Charger Disabled)
BAT = 4V VBUS = 5V 5x MODE
0.8 CURRENT (A)
0.20 INTERNAL IDEAL DIODE 0.15 OUTPUT VOLTAGE (V)
4.25
0.6 INTERNAL IDEAL DIODE ONLY 0.4
4.00 BAT = 3.4V 3.75
0.10 INTERNAL IDEAL DIODE WITH SUPPLEMENTAL EXTERNAL VISHAY Si2333 PMOS
0.2 VBUS = 0V VBUS = 5V 0 0 0.04 0.12 0.16 0.08 FORWARD VOLTAGE (V) 0.20
3556 G01
0.05
3.50
0 2.7
3.0
3.6 3.9 3.3 BATTERY VOLTAGE (V)
4.2
3556 G02
3.25
0
200
600 800 400 LOAD CURRENT (mA)
1000
3556 G03
USB Limited Battery Charge Current vs Battery Voltage
700 600 CHARGE CURRENT (mA) CHARGE CURRENT (mA) 500 400 300 200 100 VBUS = 5V RPROG = 1k RCLPROG = 3.01k 150 125 100 75 50 25 0 4.2
3556 G04
USB Limited Battery Charge Current vs Battery Voltage
25
Battery Drain Current vs Battery Voltage
IVOUT = 0A VBUS = 0V 20
VBUS = 5V RPROG = 1k RCLPROG = 3.01k
BATTERY CURRENT (A)
15
10 VBUS = 5V (SUSPEND MODE)
5 1x USB SETTING, BATTERY CHARGER SET FOR 1A 2.7 3.0 3.3 3.6 3.9 BATTERY VOLTAGE (V) 4.2
3556 G05
5x USB SETTING, BATTERY CHARGER SET FOR 1A 0 3.0 3.3 3.6 2.7 3.9 BATTERY VOLTAGE (V)
0 2.7
3.0
3.6 3.9 3.3 BATTERY VOLTAGE (V)
4.2
3556 G06
PowerPath Switching Regulator Efficiency vs Load Current
100 90 EFFICIENCY (%) 80 70 60 50 40 0.01 BAT = 3.8V 1x MODE 100 5x, 10x MODE 90 EFFICIENCY (%)
Battery Charging Efficiency vs Battery Voltage with No External Load (PBAT/PBUS)
RCLPROG = 3.01k RPROG = 1k IVOUT = 0mA 50
VBUS Current vs VBUS Voltage (Suspend)
BAT = 3.8V IVOUT = 0mA QUIESCENT CURRENT (A) 40
1x CHARGING EFFICIENCY 5x CHARGING EFFICIENCY
30
80
20
70
10
0.1 LOAD CURRENT (A)
1
3556 G07
60 2.7
3.0
3.6 3.9 3.3 BATTERY VOLTAGE (V)
4.2
3556 G08
0
0
1
3 2 BUS VOLTAGE (V)
4
5
3556 G09
3556f
7
LTC3556 TYPICAL PERFORMANCE CHARACTERISTICS
Output Voltage vs Load Current in Suspend
5.0 0.5
VBUS Current vs Load Current in Suspend
3.4 VBUS = 5V BAT = 3.3V RCLPROG = 3.01k OUTPUT VOLTAGE (V) 3.2
3.3V LDO Output Voltage vs Load Current, VBUS = 0V
BAT = 3.9V 4.2V , BAT = 3.4V BAT = 3.5V BAT = 3.6V
4.5 OUTPUT VOLTAGE (V) VBUS CURRENT (mA)
0.4
4.0
0.3
3.0
3.5
0.2
3.0
2.8
VBUS = 5V BAT = 3.3V RCLPROG = 3k 0 0.1 0.3 0.4 0.2 LOAD CURRENT (mA) 0.5
3556 G10
0.1
2.5
0
2.6 0 0.1 0.3 0.4 0.2 LOAD CURRENT (mA) 0.5
3556 G11
BAT = 3V BAT = 3.1V BAT = 3.2V BAT = 3.3V 0 5 15 20 10 LOAD CURRENT (mA) 25
3556 G12
Battery Charge Current vs Temperature
600 500 CHARGE CURRENT (mA) 400 THERMAL REGULATION 300 200 100 RPROG = 2k 10x MODE 0 -40 -20 0 4.21
Battery Charger Float Voltage vs Temperature
3.68
Low-Battery (Instant On) Output Voltage vs Temperature
BAT = 2.7V IVOUT = 100mA 5x MODE OUTPUT VOLTAGE (V) 3.66
4.20 FLOAT VOLTAGE (V)
4.19
3.64
4.18
3.62
20 40 60 80 TEMPERATURE (C)
100 120
3556 G13
4.17 -40
-15
35 10 TEMPERATURE (C)
60
85
3556 G14
3.60 -40
-15
35 10 TEMPERATURE (C)
60
85
3556 G15
Oscillator Frequency vs Temperature
2.6 15
VBUS Quiescent Current vs Temperature
VBUS = 5V IVOUT = 0A QUIESCENT CURRENT (A) 5x MODE 70
VBUS Quiescent Current in Suspend vs Temperature
IVOUT = 0A
2.4 FREQUENCY (MHz) VBUS = 5V 2.2 BAT = 3V VBUS = 0V BAT = 2.7V VBUS = 0V 1.8 -40 -15 35 10 TEMPERATURE (C)
QUIESCENT CURRENT (mA)
BAT = 3.6V VBUS = 0V
12
60
9
50
1x MODE 6
2.0
40
60
85
3556 G16
3 -40
-15
35 10 TEMPERATURE (C)
60
85
3556 G17
30 -40
-15
35 10 TEMPERATURE (C)
60
85
3556 G18
3556f
8
LTC3556 TYPICAL PERFORMANCE CHARACTERISTICS
PGOODALL, CHRG Pin Current vs Voltage (Pull-Down State)
100 PGOODALL, CHRG PIN CURRENT (mA) VBUS = 5V BAT = 3.8V BATTERY CURRENT (A) ILDO3V3 5mA/DIV 0mA VLDO3V3 20mV/DIV AC COUPLED
3556 G20
3.3V LDO Step Response (5mA to 15mA)
50
Battery Drain Current vs Temperature
BAT = 3.8V VBUS = 0V ALL REGULATORS OFF
80
40
60
30
40
20
20
BAT = 3.8V
20s/DIV
10
0
0
1 3 4 2 PGOODALL, CHRG PIN VOLTAGE (V)
5
0 -40
-15
35 10 TEMPERATURE (C)
60
85
3556 G21
3556 G19
Switching Regulators 1, 2 Pulse Skip Mode Quiescent Currents
325 VIN1,2 = 3.8V 1.95 100 90 300 INPUT CURRENT (A) VOUT1,2 = 2.5V (CONSTANT FREQUENCY) 1.90 INPUT CURRENT (mA) EFFICIENCY (%) 80
Switching Regulators 1, 2 Pulse Skip Mode Efficiency
100 VOUT1,2 = 2.5V VOUT1,2 = 1.2V VOUT1,2 = 1.8V EFFICIENCY (%) 90 80 70 60 50 40 30 20 10 VIN1,2 = 3.8V 1 10 100 LOAD CURRENT (mA) 1000
3556 G23
Switching Regulators 1, 2 Burst Mode Efficiency
VOUT1,2 = 2.5V VOUT1,2 = 1.2V VOUT1,2 = 1.8V
70 60 50 40 30 20 10
275
1.85
250
1.80
225 VOUT1,2 = 1.25V (PULSE SKIPPING) 200 -40 -15 35 10 TEMPERATURE (C) 60 85
3556 G22
1.75
1.70
0
0 0.1
VIN1,2 = 3.8V 1 10 100 LOAD CURRENT (mA) 1000
3556 G24
Switching Regulators 1, 2 Forced Burst Mode Efficiency
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 VIN1,2 = 3.8V 10 100 LOAD CURRENT (mA) 1000
3556 G25
Switching Regulators 1, 2 Load Regulation at VOUT1,2 = 1.2V
1.230 VBUS = 3.8V Burst Mode OPERATION OUTPUT VOLTAGE (V) 1.845
Switching Regulators 1, 2 Load Regulation at VOUT1,2 = 1.8V
VBUS = 3.8V Burst Mode OPERATION 1.823 PULSE SKIP MODE 1.800 FORCED Burst Mode OPERATION
VOUT1,2 = 2.5V VOUT1,2 = 1.2V VOUT1,2 = 1.8V
OUTPUT VOLTAGE (V)
1.215
1.200 PULSE SKIP MODE 1.185 FORCED Burst Mode OPERATION 1 10 100 LOAD CURRENT (mA) 1000
3556 G26
1.778
1.170 0.1
1.755 0.1
1
10 100 LOAD CURRENT (mA)
1000
3556 G27
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LTC3556 TYPICAL PERFORMANCE CHARACTERISTICS
Switching Regulators 1, 2 Load Regulation at VOUT1,2 = 2.5V
2.56 VBUS = 3.8V 14.0 13.5 OUTPUT VOLTAGE (V) 2.53 Burst Mode OPERATION PULSE SKIP MODE IVIN3 (A) 2.50 FORCED Burst Mode OPERATION 13.0 12.5 12.0 2.47 11.5 2.44 0.1 11.0 -55 -35 -15 2350 2300 -55 -35 -15 VIN3 = 3.6V
Switching Regulator 3 Burst Mode Operation Input Quiescent Current
VOUT3 = 3.3V TA = 27C VIN3 = 4.5V VIN3 = 3V 2600
Switching Regulator 3 Forward Current Limit vs Temperature
VIN3 = 3V 2550 VIN3 = 3.6V 2500 ILIMF3 (mA) VIN3 = 4.5V 2450 2400
1
10 100 LOAD CURRENT (mA)
1000
3556 G28
5
25
45
65
85 105 125
3556 G29
5
25
45
65
85 105 125
3556 G30
TEMPERATURE (C)
TEMPERATURE (C)
RDS(ON)'s for Switching Regulator 3 vs Temperature
0.30 0.25 PMOS RDS(ON) () PMOS 0.20 0.15 0.10 NMOS 0.05 VIN3 = 4.5V 0 -55 -35 -15 5 VIN3 = 3.6V 25 45 65 VIN3 = 3V VIN3 = VOUT3 = 3V VIN3 = VOUT3 = 3.6V VIN3 = VOUT3 = 4.5V 0.30 0.25 0.20 0.15 0.40 0.35 NMOS RDS(ON) () EFFICIENCY (%) 100 90 80 70 60 50 40 30 20 10 0.10 85 105 125
3556 G31
Switching Regulator 3 Efficiency vs Load Current
Burst Mode OPERATION CURVES
PWM MODE CURVES
VOUT3 = 3.3V TA = 27C VIN3 = 3V VIN3 = 3.6V VIN3 = 4.5V 1 10 100 LOAD CURRENT (mA) 1000
3556 G32
0 0.1
TEMPERATURE (C)
Switching Regulator 3 PWM Mode Efficiency vs Input Voltage
100 90 IOUT3 = 200mA IOUT3 = 1000mA REDUCTION BELOW 1A (mA) 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VOUT3 = 3.3V TA = 27C 2.7 3.1 3.5 3.9 4.3 VIN3 (V) 4.7
3556 G33
Switching Regulator 3 Reduction in Current Deliverability at Low VIN3
300 250 200 150 100 50 0 STEADY STATE LOAD START-UP WITH A RESISTIVE LOAD START-UP WITH A CURRENT SOURCE LOAD 2.7 3.1 3.5 3.9 4.3 VIN3 (V) 4.7
3556 G34
IOUT3 = 50mA
VOUT3 = 3.3V TA = 27C
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LTC3556 TYPICAL PERFORMANCE CHARACTERISTICS
Switching Regulator 3 Step Response (0mA to 300mA)
VOUT3 V = 3.8V 100mV/DIV VIN3 = 3.3V OUT3 AC COUPLED
Start-Up Sequencing with SEQ = 0V VIN1 = VIN2 = VIN3 = 4.2V All Outputs Loaded with 5mA
ENALL
1V/DIV 300mA IOUT3 200mA/ 0 DIV 100s/DIV
3556 G35
VOUT3 = 3.3V VOUT2 = 1.8V VOUT1 = 1.6V
200s/DIV
3556 G36
PIN FUNCTIONS
LDO3V3 (Pin 1): 3.3V LDO Output Pin. This pin provides a regulated, always-on, 3.3V supply voltage. LDO3V3 gets its power from VOUT. It may be used for light loads such as a watchdog microprocessor or real time clock. A 1F capacitor is required from LDO3V3 to ground. If the LDO3V3 output is not used it should be disabled by connecting it to VOUT. CLPROG (Pin 2): USB Current Limit Program and Monitor Pin. A resistor from CLPROG to ground determines the upper limit of the current drawn from the VBUS pin. A fraction of the VBUS current is sent to the CLPROG pin when the synchronous switch of the PowerPath switching regulator is on. The switching regulator delivers power until the CLPROG pin reaches 1.188V. Several VBUS current limit settings are available via user input which will typically correspond to the 500mA and 100mA USB specifications. A multilayer ceramic averaging capacitor or R-C network is required at CLPROG for filtering. NTC (Pin 3): Input to the Thermistor Monitoring Circuits. The NTC pin connects to a battery's thermistor to determine if the battery is too hot or too cold to charge. If the battery's temperature is out of range, charging is paused until it re-enters the valid range. A low drift bias resistor is required from VBUS to NTC and a thermistor is required from NTC to ground. If the NTC function is not desired, the NTC pin should be grounded. SW1 (Pin 4): Power Transmission Pin for (Buck) Switching Regulator 1. VIN1 (Pin 5): Power Input for (Buck) Switching Regulator 1. This pin will generally be connected to VOUT. A 1F MLCC capacitor is recommended on this pin. FB1 (Pin 6): Feedback Input for (Buck) Switching Regulator 1. When regulator 1's control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the I2C serial port. See Table 4. FB3 (Pin 7): Feedback Input for (Buck-Boost) Switching Regulator 3. When regulator 3's control loop is complete, this pin servos to 1 of 16 possible set-points based on the commanded value from the I2C serial port. See Table 4. VC3 (Pin 8): Output of the Error Amplifier and Voltage Compensation Node for (Buck-Boost) Switching Regulator 3. External Type I or Type III compensation (to FB3) connects to this pin. See Applications Information section for selecting buck-boost compensation components. SWAB3 (Pin 9): Switch Node for (Buck-Boost) Switching Regulator 3. Connected to internal power switches A and B. External inductor connects between this node and SWCD3. DVCC (Pin 10): Logic Supply for the I2C Serial Port. VIN3 (Pin 11): Power Input for (Buck-Boost) Switching Regulator 3. This pin will generally be connected to VOUT. A 1F (min) MLCC capacitor is recommended on this pin. VOUT3 (Pin 12): Regulated Output Voltage for (Buck-Boost) Switching Regulator 3.
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LTC3556 PIN FUNCTIONS
SCL (Pin 13): Clock Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVCC. SWCD3 (Pin 14): Switch Node for (Buck-Boost) Switching Regulator 3. Connected to internal power switches C and D. External inductor connects between this node and SWAB3. PGOODALL (Pin 15): Logic Output. This in an open-drain output which indicates that all enabled switching regulators have settled to their final value. It can be used as a power-on reset for the primary microprocessor. SDA (Pin 16): Data Input Pin for the I2C Serial Port. The I2C logic levels are scaled with respect to DVCC. FB2 (Pin 17): Feedback Input for (Buck) Switching Regulator 2. When regulator 2's control loop is complete, this pin servos to a fixed voltage of 0.8V. VIN2 (Pin 18): Power Input for (Buck) Switching Regulator 2. This pin will generally be connected to VOUT. A 1F MLCC capacitor is recommended on this pin. SW2 (Pin 19): Power Transmission Pin for (Buck) Switching Regulator 2. PROG (Pin 20): Charge Current Program and Charge Current Monitor Pin. Connecting a resistor from PROG to ground programs the charge current. If sufficient input power is available in constant-current mode, this pin servos to 1V. The voltage on this pin always represents the actual charge current. CHRG (Pin 21): Open-Drain Charge Status Output. The CHRG pin indicates the status of the battery charger. Four possible states are represented by CHRG: charging, not charging, unresponsive battery and battery temperature out of range. CHRG is modulated at 35kHz and switches between a low and a high duty cycle for easy recognition by either humans or microprocessors. See Table 1. CHRG requires a pull-up resistor and/or LED to provide indication. GATE (Pin 22): Analog Output. This pin controls the gate of an optional external P-channel MOSFET transistor used to supplement the ideal diode between VOUT and BAT. The external ideal diode operates in parallel with the internal ideal diode. The source of the P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. If the external ideal diode FET is not used, GATE should be left floating. BAT (Pin 23): Single Cell Li-Ion Battery Pin. Depending on available VBUS power, a Li-Ion battery on BAT will either deliver power to VOUT through the ideal diode or be charged from VOUT via the battery charger. VOUT (Pin 24): Output Voltage of the Switching PowerPath Controller and Input Voltage of the Battery Charger. The majority of the portable product should be powered from VOUT. The LTC3556 will partition the available power between the external load on VOUT and the internal battery charger. Priority is given to the external load and any extra power is used to charge the battery. An ideal diode from BAT to VOUT ensures that VOUT is powered even if the load exceeds the allotted power from VBUS or if the VBUS power source is removed. VOUT should be bypassed with a low impedance ceramic capacitor. VBUS (Pin 25): Primary Input Power Pin. This pin delivers power to VOUT via the SW pin by drawing controlled current from a DC source such as a USB port or wall adapter. SW (Pin 26): Power Transmission Pin for the USB Power Path. The SW pin delivers power from VBUS to VOUT via the step-down switching regulator. A 3.3H inductor should be connected from SW to VOUT. SEQ (Pin 27): Sequence Select Logic Input. Three-state input which determines start-up sequence after ENALL is asserted. If tied to GND, start-up sequence is: Buck 1 Buck 2 Buck-Boost If tied to VOUT , start-up sequence is: Buck 1 Buck-Boost Buck 2 If left floating, start-up sequence is: Buck-Boost Buck 1 Buck 2 ENALL (Pin 28): Enable All Logic Input. Enables all three switching regulators in sequence according to the state of the SEQ pin. Active high. Has a 5.5M internal pull-down resistor. Alternately, all switching regulators can be individually enabled via the I2C serial port. Exposed Pad (Pin 29): Ground. The Exposed Pad should be connected to a continuous ground plane on the second layer of the printed circuit board by several vias directly under the LTC3556.
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LTC3556 BLOCK DIAGRAM
VBUS 25 2.25MHz PowerPath SWITCHING REGULATOR SUSPEND LDO 500A CC/CV CHARGER 0.3V 3.6V 20 PROG 5 VIN1 4 SW1 3.3V LDO 24 VOUT
26 SW 1 LDO3V3
+
CLPROG 2 IDEAL
- + -
15mV
22 GATE
NTC 3
BATTERY TEMPERATURE MONITOR
1.188V
CHRG 21 CHARGE STATUS D/A 4
EN1 400mA 2.25MHz (BUCK) SWITCHING REGULATOR 1
EN2 PGOODALL 15 POWER GOOD 400mA 2.25MHz (BUCK) SWITCHING REGULATOR 2
EN3
SEQ 27
MASTER LOGIC AND SEQUENCER
D/A 4
ENALL 28 DVCC 10 SDA 16 SCL 13 29 GND I2C PORT
-+
A 1A 2.25MHz (BUCK-BOOST) SWITCHING REGULATOR 3 B D C
+ + -
+ -
23 BAT
6 FB1
18 VIN2 19 SW2
17 FB2 11 VIN3 9 SWAB3
12 VOUT3 14 SWCD3
7 FB3 8 VC3
3556 BD
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LTC3556 TIMING DIAGRAM
I2C Timing Diagram
DATA BYTE A ADDRESS 0 START SDA 0 0 0 1 0 0 1 0 ACK ACK ACK 0 0 1 0 0 1 WR 0 A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 STOP DATA BYTE B
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SDA tSU, DAT tLOW SCL tHD, STA START CONDITION tr tHIGH tf REPEATED START CONDITION tSP STOP CONDITION START CONDITION tHD, DAT tSU, STA tHD, STA tBUF tSU, STO
3556 TD
OPERATION
Introduction The LTC3556 is a highly integrated power management IC which includes a high efficiency switch mode PowerPath controller, a battery charger, an ideal diode, an always-on LDO, two 400mA buck switching regulators and a 1A buckboost switching regulator. The entire chip is controllable via an I2C serial port. Designed specifically for USB applications, the PowerPath controller incorporates a precision average input current step-down switching regulator to make maximum use of the allowable USB power. Because power is conserved, the LTC3556 allows the load current on VOUT to exceed the current drawn by the USB port without exceeding the USB load specifications. The PowerPath switching regulator and battery charger communicate to ensure that the input current never violates the USB specifications. The ideal diode from BAT to VOUT guarantees that ample power is always available to VOUT even if there is insufficient or absent power at VBUS. An "always-on" LDO provides a regulated 3.3V from available power at VOUT. Drawing very little quiescent current, this LDO will be on at all times and can be used to supply up to 25mA. The three switching regulators can be enabled together in any desired sequence via the ENALL and SEQ pins or can be independently enabled via the I2C serial port. Under I2C control, one of the 400mA bucks and the 1A buck-boost have adjustable set-points so that voltages can be reduced when high processor performance is not needed. Along with constant frequency PWM mode, all three switching regulators have a low power burst-only mode setting for significantly reduced quiescent current under light load conditions. Additionally, the 400mA bucks can be configured for automatic Burst Mode operation or LDO mode. High Efficiency Switching PowerPath Controller Whenever VBUS is available and the PowerPath switching regulator is enabled, power is delivered from VBUS to VOUT via SW. VOUT drives the combination of the external load (including switching regulators 1, 2 and 3) and the battery charger. If the combined load does not exceed the PowerPath switching regulator's programmed input current limit, VOUT will track 0.3V above the battery (Bat-Track). By keeping the voltage across the battery charger low, efficiency is optimized because power lost to the linear battery charger is minimized. Power available to the external load is therefore optimized.
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LTC3556 OPERATION
If the combined load at VOUT is large enough to cause the switching power supply to reach the programmed input current limit, the battery charger will reduce its charge current by that amount necessary to enable the external load to be satisfied. Even if the battery charge current is set to exceed the allowable USB current, the USB specification will not be violated. The switching regulator will limit the average input current so that the USB specification is never violated. Furthermore, load current at VOUT will always be prioritized and only remaining available power will be used to charge the battery. If the voltage at BAT is below 3.3V, or the battery is not present and the load requirement does not cause the switching regulator to exceed the USB specification, VOUT will regulate at 3.6V, thereby providing instant-on operation. If the load exceeds the available power, VOUT will drop to a voltage between 3.6V and the battery voltage. If there is no battery present when the load exceeds the available USB power, VOUT can drop toward ground. The power delivered from VBUS to VOUT is controlled by a 2.25MHz constant-frequency step-down switching regulator. To meet the USB maximum load specification, the switching regulator includes a control loop which ensures that the average input current is below the level programmed at CLPROG. The current at CLPROG is a fraction (hCLPROG-1) of the VBUS current. When a programming resistor and an averaging capacitor are connected from CLPROG to GND, the voltage on CLPROG represents the average input current of the switching regulator. When the input current approaches the programmed limit, CLPROG reaches VCLPROG, 1.188V and power out is held constant. The input current limit is programmed by the B1 and B0 bits of the I2C serial port. It can be configured to limit average input current to one of several possible settings as well as be deactivated (USB Suspend). The input current limit will be set by the VCLPROG servo voltage and the resistor on CLPROG according to the following expression: IVBUS = IVBUSQ + VCLPROG * (hCLPROG + 1 ) RCLPROG
4.5 4.2 3.9 VOUT (V) NO LOAD 3.6 300mV 3.3 3.0 2.7 2.4 2.4
2.7
3.0
3.6 3.3 BAT (V)
3.9
4.2
3556 F01
Figure 1. VOUT vs BAT
Ideal Diode from BAT to VOUT The LTC3556 has an internal ideal diode as well as a controller for an optional external ideal diode. The ideal diode controller is always on and will respond quickly whenever VOUT drops below BAT. If the load current increases beyond the power allowed from the switching regulator, additional power will be pulled from the battery via the ideal diode. Furthermore, if power to VBUS (USB or wall power) is removed, then all of the application power will be provided by the battery via the ideal diode. The transition from input power to battery power at VOUT will be quick enough to allow only the 10F capacitor to keep VOUT from drooping. The ideal diode consists of a precision amplifier that enables a large onchip P-channel MOSFET transistor whenever the voltage at
2200 2000 1800 1600 CURRENT (mA) 1400 1200 1000 800 600 400 200 0 0 60 120 180 240 300 360 420 480 FORWARD VOLTAGE (mV) (BAT - VOUT)
3556 F02
VISHAY Si2333 OPTIONAL EXTERNAL IDEAL DIODE
LTC3556 IDEAL DIODE
ON SEMICONDUCTOR MBRM120LT3
Figure 1 shows the range of possible voltages at VOUT as a function of battery voltage.
Figure 2. Ideal Diode Operation
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LTC3556 OPERATION
VOUT is approximately 15mV (VFWD) below the voltage at BAT. The resistance of the internal ideal diode is approximately 180m. If this is sufficient for the application, then no external components are necessary. However, if more conductance is needed, an external P-channel MOSFET transistor can be added from BAT to VOUT. When an external P-channel MOSFET transistor is present, the GATE pin of the LTC3556 drives its gate for automatic ideal diode control. The source of the external P-channel MOSFET should be connected to VOUT and the drain should be connected to BAT. Capable of driving a 1nF load, the GATE pin can control an external P-channel MOSFET transistor having an on-resistance of 40m or lower. Suspend LDO If the LTC3556 is configured for USB suspend mode, the switching regulator is disabled and the suspend LDO provides power to the VOUT pin (presuming there is power available to VBUS). This LDO will prevent the battery from running down when the portable product has access to a suspended USB port. Regulating at 4.6V, this LDO only becomes active when the switching converter is disabled (suspended). To remain compliant with the USB specification, the input to the LDO is current limited so that it will not exceed the 500A low power suspend specification. If the load on VOUT exceeds the suspend current limit, the additional current will come from the battery via the ideal diode. 3.3V Always-On Supply The LTC3556 includes a low quiescent current low dropout regulator that is always powered. This LDO can be used to provide power to a system pushbutton controller, standby microcontroller or real time clock. Designed to deliver up to 25mA, the always-on LDO requires at least a 1F low impedance ceramic bypass capacitor for compensation. The LDO is powered from VOUT , and therefore will enter dropout at loads less than 25mA as VOUT falls near 3.3V. If the LDO3V3 output is not used, it should be disabled by connecting it to VOUT. VBUS Undervoltage Lockout (UVLO) An internal undervoltage lockout circuit monitors VBUS and keeps the PowerPath switching regulator off until VBUS rises above 4.30V and is about 200mV above the battery voltage. Hysteresis on the UVLO turns off the regulator if VBUS drops below 4.00V or to within 50mV of BAT. When this happens, system power at VOUT will be drawn from the battery via the ideal diode.
TO USB OR WALL ADAPTER
25
VBUS
SW
26
3.5V TO (BAT + 0.3V) TO SYSTEM LOAD
PWM AND GATE DRIVE ISWITCH/ hCLPROG CONSTANT CURRENT CONSTANT VOLTAGE BATTERY CHARGER 15mV 0.3V 3.6V IDEAL DIODE
VOUT
24
+ - + -
GATE
22
OPTIONAL EXTERNAL IDEAL DIODE PMOS
2
1.188V
AVERAGE INPUT CURRENT LIMIT CONTROLLER
AVERAGE OUTPUT VOLTAGE LIMIT CONTROLLER
3556 F03
Figure 3. PowerPath Block Diagram
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16
+ + -
+ -
CLPROG
+-
BAT
23
+
SINGLE CELL Li-Ion
LTC3556 OPERATION
Battery Charger The LTC3556 includes a constant-current/constant-voltage battery charger with automatic recharge, automatic termination by safety timer, low voltage trickle charging, bad cell detection and thermistor sensor input for out-oftemperature charge pausing. Battery Preconditioning When a battery charge cycle begins, the battery charger first determines if the battery is deeply discharged. If the battery voltage is below VTRKL, typically 2.85V, an automatic trickle charge feature sets the battery charge current to 10% of the programmed value. If the low voltage persists for more than 1/2 hour, the battery charger automatically terminates and indicates via the CHRG pin that the battery was unresponsive. Once the battery voltage is above 2.85V, the battery charger begins charging in full power constant-current mode. The current delivered to the battery will try to reach 1022V/ RPROG. Depending on available input power and external load conditions, the battery charger may or may not be able to charge at the full programmed rate. The external load will always be prioritized over the battery charge current. The USB current limit programming will always be observed and only additional power will be available to charge the battery. When system loads are light, battery charge current will be maximized. Charge Termination The battery charger has a built-in safety timer. When the voltage on the battery reaches the pre-programmed float voltage of 4.200V, the battery charger will regulate the battery voltage and the charge current will decrease naturally. Once the battery charger detects that the battery has reached 4.200V, the four hour safety timer is started. After the safety timer expires, charging of the battery will discontinue and no more current will be delivered. Automatic Recharge After the battery charger terminates, it will remain off drawing only microamperes of current from the battery. If the portable product remains in this state long enough, the battery will eventually self discharge. To ensure that the battery is always topped off, a charge cycle will automatically begin when the battery voltage falls below 4.1V. In the event that the safety timer is running when the battery voltage falls below 4.1V, it will reset back to zero. To prevent brief excursions below 4.1V from resetting the safety timer, the battery voltage must be below 4.1V for more than 1.3ms. The charge cycle and safety timer will also restart if the VBUS UVLO cycles low and then high (e.g., VBUS is removed and then replaced), or if the battery charger is cycled on and off by the I2C port. Charge Current The charge current is programmed using a single resistor from PROG to ground. 1/1022th of the battery charge current is sent to PROG which will attempt to servo to 1.000V. Thus, the battery charge current will try to reach 1022 times the current in the PROG pin. The program resistor and the charge current are calculated using the following equations: RPROG = 1022V 1022V , ICHRG = ICHRG RPROG
In either the constant-current or constant-voltage charging modes, the voltage at the PROG pin will be proportional to the actual charge current delivered to the battery. Therefore, the actual charge current can be determined at any time by monitoring the PROG pin voltage and using the following equation: IBAT = VPROG * 1022 RPROG
In many cases, the actual battery charge current, IBAT , will be lower than ICHRG due to limited input power available and prioritization with the system load drawn from VOUT. Charge Status Indication The CHRG pin indicates the status of the battery charger. Four possible states are represented by CHRG which include charging, not charging, unresponsive battery, and battery temperature out of range. The signal at the CHRG pin can be easily recognized as one of the above four states by either a human or a microprocessor. An open-drain output, the CHRG pin can
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LTC3556 OPERATION
drive an indicator LED through a current limiting resistor for human interfacing or simply a pull-up resistor for microprocessor interfacing. To make the CHRG pin easily recognized by both humans and microprocessors, the pin is either Low for charging, High for not charging, or it is switched at high frequency (35kHz) to indicate the two possible faults, unresponsive battery and battery temperature out of range. When charging begins, CHRG is pulled low and remains low for the duration of a normal charge cycle. When charging is complete, i.e., the BAT pin reaches 4.200V and the charge current has dropped to one tenth of the programmed value, the CHRG pin is released (Hi-Z). If a fault occurs, the pin is switched at 35kHz. While switching, its duty cycle is modulated between a high and low value at a very low frequency. The low and high duty cycles are disparate enough to make an LED appear to be on or off thus giving the appearance of "blinking". Each of the two faults has its own unique "blink" rate for human recognition as well as two unique duty cycles for machine recognition. The CHRG pin does not respond to the C/10 threshold if the LTC3556 is in VBUS current limit. This prevents false end of charge indications due to insufficient power available to the battery charger. Table 1 illustrates the four possible states of the CHRG pin when the battery charger is active.
Table 1. CHRG Signal STATUS Charging Not Charging NTC Fault Bad Battery FREQUENCY 0Hz 0Hz 35kHz 35kHz MODULATION (BLINK) FREQUENCY 0Hz (Lo-Z) 0Hz (Hi-Z) 1.5Hz at 50% 6.1Hz at 50% DUTY CYCLES 100% 0% 6.25%, 93.75% 12.5%, 87.5%
pin gives the battery fault indication. For this fault, a human would easily recognize the frantic 6.1Hz "fast" blink of the LED while a microprocessor would be able to decode either the 12.5% or 87.5% duty cycles as a bad battery fault. Note that the LTC3556 is a 3-terminal PowerPath product where system load is always prioritized over battery charging. Due to excessive system load, there may not be sufficient power to charge the battery beyond the trickle charge threshold voltage within the bad battery timeout period. In this case, the battery charger will falsely indicate a bad battery. System software may then reduce the load and reset the battery charger to try again. Although very improbable, it is possible that a duty cycle reading could be taken at the bright-dim transition (low duty cycle to high duty cycle). When this happens the duty cycle reading will be precisely 50%. If the duty cycle reading is 50%, system software should disqualify it and take a new duty cycle reading. NTC Thermistor The battery temperature is measured by placing a negative temperature coefficient (NTC) thermistor close to the battery pack. To use this feature, connect the NTC thermistor, RNTC, between the NTC pin and ground and a resistor, RNOM, from VBUS to the NTC pin. RNOM should be a 1% resistor with a value equal to the value of the chosen NTC thermistor at 25C (R25). A 100k thermistor is recommended since thermistor current is not measured by the LTC3556 and will have to be budgeted for USB compliance. The LTC3556 will pause charging when the resistance of the NTC thermistor drops to 0.54 times the value of R25 or approximately 54k. For Vishay "Curve 1" thermistor, this corresponds to approximately 40C. If the battery charger is in constant-voltage (float) mode, the safety timer also pauses until the thermistor indicates a return to a valid temperature. As the temperature drops, the resistance of the NTC thermistor rises. The LTC3556 is also designed to pause charging when the value of the NTC thermistor increases to 3.25 times the value of R25. For Vishay "Curve 1" this resistance, 325k, corresponds to approximately 0C. The hot and cold comparators each
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An NTC fault is represented by a 35kHz pulse train whose duty cycle alternates between 6.25% and 93.75% at a 1.5Hz rate. A human will easily recognize the 1.5Hz rate as a "slow" blinking which indicates the out-of-range battery temperature while a microprocessor will be able to decode either the 6.25% or 93.75% duty cycles as an NTC fault. If a battery is found to be unresponsive to charging (i.e., its voltage remains below 2.85V for 1/2 hour), the CHRG
18
LTC3556 OPERATION
have approximately 3C of hysteresis to prevent oscillation about the trip point. Grounding the NTC pin disables the NTC charge pausing function. Thermal Regulation To optimize charging time, an internal thermal feedback loop may automatically decrease the programmed charge current. This will occur if the die temperature rises to approximately 110C. Thermal regulation protects the LTC3556 from excessive temperature due to high power operation or high ambient thermal conditions and allows the user to push the limits of the power handling capability with a given circuit board design without risk of damaging the LTC3556 or external components. The benefit of the LTC3556 thermal regulation loop is that charge current can be set according to actual conditions rather than worst-case conditions with the assurance that the battery charger will automatically reduce the current in worst-case conditions. I2C Interface The LTC3556 may receive commands from a host (master) using the standard I2C 2-wire interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 I2C accelerator, are required on these lines. The LTC3556 is a receive-only (slave) device. The I2C control signals, SDA and SCL are scaled internally to the DVCC supply. DVCC should be connected to the same power supply as the microcontroller generating the I2C signals. The I2C port has an undervoltage lockout on the DVCC pin. When DVCC is below approximately 1V, the I2C serial port is cleared and switching regulators 1 and 3 are set to full scale. Bus Speed The I2C port is designed to be operated at speeds of up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted. Start and Stop Condition A bus master signals the beginning of a communication to a slave device by transmitting a Start condition. A Start condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a Stop condition by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Byte Format Each byte sent to the LTC3556 must be eight bits long followed by an extra clock cycle for the Acknowledge bit to be returned by the LTC3556. The data should be sent to the LTC3556 most significant bit (MSb) first. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active low) generated by the slave (LTC3556) lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (high) during the Acknowledge clock cycle. The slave receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable Low during the High period of this clock pulse. Slave Address The LTC3556 responds to only one 7-bit address which has been factory programmed to 0001001. The LSb of the address byte is 1 for Read and 0 for Write. This device is write only corresponding to an address byte of 00010010 (0x12). If the correct seven bit address is given but the R/W bit is 1, the LTC3556 will not respond.
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LTC3556 OPERATION
Table 2. I2C Serial Port Mapping (Defaults to 0xFF00 in Reset State or if DVCC = 0V)
A7 A6 A5 A4 A3 A2 A1 A0 B7 Disable Battery Charger B6 B5 B4 B3 B2 B1 B0 Switching Regulator 1 Voltage (See Table 4) Switching Regulator 3 Voltage (See Table 4) Switching Regulator Enable Enable Enable Input Current Limit Modes (See Table 5) Regulator Regulator Regulator (See Table 3) 1 2 3
Table 3. USB Current Limit Settings
B1 0 1 0 1 B0 1 1 0 0 USB SETTING 10x Mode (Wall 1A Limit) 5x Mode (USB 500mA Limit) 1x Mode (USB 100mA Limit) Suspend
Bus Write Operation The master initiates communication with the LTC3556 with a Start condition and a 7-bit address followed by the Write Bit R/W = 0. If the address matches that of the LTC3556, the LTC3556 returns an Acknowledge. The master should then deliver the most significant data byte. Again the LTC3556 acknowledges and the cycle is repeated for a total of one address byte and two data bytes. Each data byte is transferred to an internal holding latch upon the return of an Acknowledge. After both data bytes have been transferred to the LTC3556, the master may terminate the communication with a Stop condition. Alternatively, a Repeat-Start condition can be initiated by the master and another chip on the I2C bus can be addressed. This cycle can continue indefinitely and the LTC3556 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global Stop condition can be sent and the LTC3556 will update its command latch with the data that it had received. In certain circumstances the data on the I2C bus may become corrupted. In these cases the LTC3556 responds appropriately by preserving only the last set of complete data that it has received. For example, assume the LTC3556 has been successfully addressed and is receiving data when a Stop condition mistakenly occurs. The LTC3556 will ignore this stop condition and will not respond until a new Start condition, correct address, new set of data and Stop condition are transmitted. Likewise, with only one exception, if the LTC3556 was previously addressed and sent valid data but not updated with a Stop, it will respond to any Stop that appears on the bus, independent of the number of Repeat-Starts that have occurred. If a Repeat-Start is given and the LTC3556 successfully acknowledges its address and first byte, it will not respond to a Stop until both bytes of the new data have been received and acknowledged.
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Table 4. Switching Regulator Servo Voltage
A7 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A5 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A4 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SWITCHING REGULATOR 1 SERVO VOLTAGE SWITCHING REGULATOR 3 SERVO VOLTAGE 0.425V 0.450V 0.475V 0.500V 0.525V 0.550V 0.575V 0.600V 0.625V 0.650V 0.675V 0.700V 0.725V 0.750V 0.775V 0.800V
Table 5. Switching Regulator Modes
B6 0 1 0 1 MODE OF (BUCK) SWITCHING MODE OF (BUCK-BOOST) B5 REGULATORS 1 AND 2 SWITCHING REGULATOR 3 0 1 1 0 Pulse Skip Mode Burst Mode Operation Forced Burst Mode Operation LDO Mode Burst Mode Operation PWM Mode
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LTC3556 OPERATION
Disabling the I2C Port The I2C serial port can be disabled by grounding the DVCC pin. In this mode, control automatically passes to the individual logic input pins ENALL and SEQ. However, considerable functionality is not available in this mode such as the ability to independently enable the three switching regulators and disable the battery charger. In addition, with the I2C port disabled, both programmable switching regulators default to a fixed servo voltage of 0.8V, both 400mA bucks default to pulse skip mode, the 1A buckboost defaults to PWM mode, and the USB input current limit defaults to 1x mode (100mA Limit). PGOODALL Pin The PGOODALL pin is an open-drain output used to indicate that all enabled switching regulators have reached their final voltage. PGOODALL remains low impedance until the last enabled regulator in the sequence reaches 92% of its regulation value. A 230ms delay is included to allow a system microcontroller ample time to reset itself. PGOODALL may be used as a power-on reset to the microprocessor powered by one (or more) of the three regulated outputs. PGOODALL is an open-drain output and requires a pull-up resistor to the input voltage of the monitoring microprocessor or another appropriate power source. 400mA Step-Down Switching Regulators The LTC3556 contains two 2.25MHz step-down (buck) constant-frequency current mode switching regulators. Each buck regulator can provide up to 400mA of output current. Both buck regulators can be programmed for a minimum output voltage of 0.8V and can be used to power a microcontroller core, microcontroller I/O, memory, disk drive or other logic circuitry. One of the buck regulators has I2C programmable set-points for on-the-fly power savings. Both buck converters support 100% duty cycle operation (low dropout mode) when their input voltage drops very close to their output voltage. To suit a variety of applications, selectable mode functions can be used to trade off noise for efficiency. Four modes are available to control the operation of the LTC3556's buck regulators. At moderate to heavy loads, the pulse skip mode provides the least noise switching solution. At lighter loads, either Burst Mode operation, forced Burst Mode operation or LDO mode may be selected. The buck regulators include soft-start to limit inrush current when powering on, shortcircuit current protection and switch node slew limiting circuitry to reduce radiated EMI. No external compensation components are required. The operating mode of the buck regulators can be set by I2C control and defaults to pulse skip mode if the I2C port is not used. Both buck converters are enabled (along with the buck-boost) when the ENALL pin is asserted or each may be individually enabled by the I2C port. Buck regulator 1 has a programmable feedback servo voltage via I2C control (which defaults to 800mV if the I2C port is not used) whereas buck regulator 2 has a fixed feedback servo voltage of 800mV. The buck regulator input supplies VIN1 and VIN2 will generally be connected to the system load pin VOUT. Buck Regulator Output Voltage Programming Both buck regulators can be programmed for output voltages greater than 0.8V. The full-scale output voltage for each buck regulator is programmed using a resistor divider from the buck regulator output connected to the feedback pins (FB1 and FB2) such that: R1 VOUTX = VFBX + 1 R2 where VFBX ranges from 0.425V to 0.8V for buck regulator 1 and VFBX is fixed at 0.8V for buck regulator 2. See Figure 4. Typical values for R1 are in the range of 40k to 1M. The capacitor, CFB , cancels the pole created by feedback resistors and the input capacitance of the FBx pin and also helps to improve transient response for output voltages much
VINx SWx LTC3556 FBx R2 GND
3556 F04
L VOUTx CFB R1 COUT
Figure 4. Buck Converter Application Circuit
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LTC3556 OPERATION
greater than 0.8V. A variety of capacitor sizes can be used for CFB but a value of 10pF is recommended for most applications. Experimentation with capacitor sizes between 2pF and 22pF may yield improved transient response. Buck Regulator Operating Modes The LTC3556's buck regulators include four possible operating modes to meet the noise/power needs of a variety of applications. In pulse skip mode, an internal latch is set at the start of every cycle which turns on the main P-channel MOSFET switch. During each cycle, a current comparator compares the peak inductor current to the output of an error amplifier. The output of the current comparator resets the internal latch which causes the main P-channel MOSFET switch to turn off and the N-channel MOSFET synchronous rectifier to turn on. The N-channel MOSFET synchronous rectifier turns off at the end of the 2.25MHz cycle or if the current through the N-channel MOSFET synchronous rectifier drops to zero. Using this method of operation, the error amplifier adjusts the peak inductor current to deliver the required output power. All necessary compensation is internal to the switching regulator requiring only a single ceramic output capacitor for stability. At light loads in PWM mode, the inductor current may reach zero on each pulse which will turn off the N-channel MOSFET synchronous rectifier. In this case, the switch node (SW) goes high impedance and the switch node voltage will "ring." This is discontinuous mode operation and is normal behavior for a switching regulator. At very light loads in pulse skip mode, the buck regulators will automatically skip pulses as needed to maintain output regulation. At high duty cycles (VOUTx > VINx/2) it is possible for the inductor current to reverse, causing the buck regulator to operate continuously at light loads. This is normal and regulation is maintained, but the supply current will increase to several milliamperes due to continuous switching. In forced Burst Mode operation, the buck regulators use a constant-current algorithm to control the inductor current. By controlling the inductor current directly and using a hysteretic control loop, both noise and switching losses are minimized. In this mode output power is limited. While in forced Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The step-down converter then goes into sleep mode, during which the output capacitor provides the load cur rent. In sleep mode, most of the regulator's circuitry is powered down, helping conserve battery power. When the output voltage drops below a predetermined value, the buck regulator circuitry is powered on and another burst cycle begins. The duration for which the buck regulator operates in sleep mode depends on the load current. The sleep time decreases as the load current increases. The maximum output current in forced Burst Mode operation is about 100mA for buck regulators 1 and 2. The buck regulators will not enter sleep mode if the maximum output current is exceeded in forced Burst Mode operation and the output will drop out of regulation. Forced Burst Mode operation provides a significant improvement in efficiency at light loads at the expense of higher output ripple when compared to pulse skip mode. For many noise-sensitive systems, forced Burst Mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e., when the device is in low power standby mode). The I2C port can be used to enable or disable forced Burst Mode operation at any time, offering both low noise and low power operation when they are needed. In Burst Mode operation, the buck regulator automatically switches between fixed frequency PWM operation and hysteretic control as a function of the load current. At light loads, the buck regulators operate in hysteretic mode in much the same way as described for the forced Burst Mode operation. Burst Mode operation provides slightly less output ripple at the expense of slightly lower efficiency than forced Burst Mode operation. At heavy loads, the buck regulator operates in the same manner as pulse skip operation does at high loads. For applications that can tolerate some output ripple at low output currents, Burst Mode operation provides better efficiency than pulse skip at light loads while still providing the full specified output current of the buck regulator. Finally, the buck regulators have an LDO mode that gives a DC option for regulating their output voltages. In LDO mode, the buck regulators are converted to linear regula3556f
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LTC3556 OPERATION
tors and deliver continuous power from their SWx pins through their respective inductors. This mode gives the lowest possible output noise as well as low quiescent current at light loads. The buck regulators allow mode transition on the fly, providing seamless transition between modes even under load. This allows the user to switch back and forth between modes to reduce output ripple or increase low current efficiency as needed. Buck Regulator in Shutdown The buck regulators are in shutdown when not enabled for operation. In shutdown, all circuitry in the buck regulator is disconnected from the buck regulator input supply leaving only a few nanoamperes of leakage current. The buck regulator outputs are individually pulled to ground through a 10k resistor on the switch pins (SW1 and SW2) when in shutdown. Buck Regulator Dropout Operation It is possible for a buck regulator's input voltage, VINX, to approach its programmed output voltage (e.g., a battery voltage of 3.4V with a programmed output voltage of 3.3V). When this happens, the PMOS switch duty cycle increases until it is turned on continuously at 100%. In this dropout condition, the respective output voltage equals the buck regulator's input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. Buck Regulator Soft-Start Operation Soft-start is accomplished by gradually increasing the peak inductor current for each buck regulator over a 500s period. This allows each output to rise slowly, helping minimize the battery surge current. A soft-start cycle occurs whenever a given buck regulator is enabled, or after a fault condition has occurred (thermal shutdown or UVLO). A soft-start cycle is not triggered by changing operating modes. This allows seamless output operation when transitioning between forced Burst Mode, Burst Mode, pulse skip mode or LDO operation. Buck Regulator Switching Slew Rate Control The buck regulators contain new patent pending circuitry to limit the slew rate of the switch node (SW1 and SW2). This new circuitry is designed to transition the switch node over a period of a couple of nanoseconds, significantly reducing radiated EMI and conducted supply noise. Low Supply Operation The LTC3556 incorporates an undervoltage lockout circuit on VOUT which shuts down both buck regulators (as well as the buck-boost) when VOUT drops below VOUTUVLO. This UVLO prevents unstable operation. Buck-Boost DC/DC Switching Regulator The LTC3556 contains a 2.25MHz constant-frequency voltage mode buck-boost switching regulator. The regulator provides up to 1A of output load current. The buck-boost can be programmed to a minimum output voltage of 2.5V and can be used to power a microcontroller core, microcontroller I/O, memory, disk drive or other logic circuitry. When controlled by I2C, the buck-boost has programmable set-points for on-the-fly power savings. To suit a variety of applications, a selectable mode function allows the user to trade off noise for efficiency. Two modes are available to control the operation of the LTC3556's buck-boost regulator. At moderate to heavy loads, the constant frequency PWM mode provides the least noise switching solution. At lighter loads Burst Mode operation may be selected. The full-scale output voltage is programmed by a user-supplied resistive divider returned to the FB3 pin. An error amplifier compares the divided output voltage with a reference and adjusts the compensation voltage accordingly until the FB3 has stabilized to the selected reference voltage (0.425V to 0.8V). The buck-boost regulator also includes a soft-start to limit inrush current and voltage overshoot when powering on, short circuit current protection, and switch node slew limiting circuitry for reduced radiated EMI.
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LTC3556 OPERATION
Input Current Limit The input current limit comparator will shut the input PMOS switch off once current exceeds 2.5A (typical). The 2.5A input current limit also protects against a grounded VOUT3 node. Output Overvoltage Protection If the FB3 node were inadvertently shorted to ground, then the output would increase indefinitely with the maximum current that could be sourced from VIN3. The LTC3556 protects against this by shutting off the input PMOS if the output voltage exceeds 5.6V (typical). Low Output Voltage Operation When the output voltage is below 2.65V (typical) during startup, Burst Mode operation is disabled and switch D is turned off (allowing forward current through the well diode and limiting reverse current to 0mA). Buck-Boost Regulator PWM Operating Mode In PWM mode the voltage seen at FB3 is compared to the selected reference voltage (0.425V to 0.8V). From the FB3 voltage an error amplifier generates an error signal seen at VC3. This error signal commands PWM waveforms that modulate switches A, B, C and D. Switches A and B operate synchronously as do switches C and D. If VIN3 is significantly greater than the programmed VOUT3, then the converter will operate in buck mode. In this case switches A and B will be modulated, with switch D always on (and switch C always off), to step down the input voltage to the programmed output. If VIN3 is significantly less than the programmed VOUT3, then the converter will operate in boost mode. In this case switches C and D are modulated, with switch A always on (and switch B always off), to step up the input voltage to the programmed output. If VIN3 is close to the programmed VOUT3, then the converter will operate in 4-switch mode. In this mode the switches sequence through the pattern of AD, AC, BD to either step the input voltage up or down to the programmed output. Buck-Boost Regulator Burst Mode Operation In Burst Mode operation, the buck-boost regulator uses a hysteretic FB3 voltage algorithm to control the output voltage. By limiting FET switching and using a hysteretic control loop, switching losses are greatly reduced. In this mode output current is limited to 50mA typical. While operating in Burst Mode operation, the output capacitor is charged to a voltage slightly higher than the regulation point. The buck-boost converter then goes into a sleep state, during which the output capacitor provides the load current. The output capacitor is charged by charging the inductor until the input current reaches 250mA typical and then discharging the inductor until the reverse current reaches 0mA typical. This process is repeated until the feedback voltage has charged to 6mV above the regulation point. In the sleep state, most of the regulator's circuitry is powered down, helping to conserve battery power. When the feedback voltage drops 6mV below the regulation point, the switching regulator circuitry is powered on and another burst cycle begins. The duration for which the regulator sleeps depends on the load current and output capacitor value. The sleep time decreases as the load current increases. The maximum load current in Burst Mode operation is 50mA typical. The buck-boost regulator will not go to sleep if the current is greater than 50mA, and if the load current increases beyond this point while in Burst Mode operation the output will lose regulation. Burst Mode operation provides a significant improvement in efficiency at light loads at the expense of higher output ripple when compared to PWM mode. For many noise-sensitive systems, Burst Mode operation might be undesirable at certain times (i.e., during a transmit or receive cycle of a wireless device), but highly desirable at others (i.e., when the device is in low power standby mode). The B6 and B5 bits of the I2C port are used to enable or disable Burst Mode operation at any time, offering both low noise and low power operation when they are needed.
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LTC3556 OPERATION
Buck-Boost Regulator Soft-Start Operation Soft-start is accomplished by gradually increasing the reference voltage input to the error amplifier over a 0.5ms (typical) period. This limits transient inrush currents during start-up because the output voltage is always "in regulation." Ramping the reference voltage input also limits the rate of increase in the VC3 voltage which helps minimize output overshoot during start-up. A soft-start cycle occurs whenever the buck-boost is enabled, or after a fault condition has occurred (thermal shutdown or UVLO). A soft-start cycle is not triggered by changing operating modes. This allows seamless operation when transitioning between Burst Mode operation and PWM mode. Low Supply Operation The LTC3556 incorporates an undervoltage lockout circuit on VOUT (connected to VIN3) which shuts down the buckboost regulator when VOUT drops below 2.6V. This UVLO prevents unstable operation.
APPLICATIONS INFORMATION
CLPROG Resistor and Capacitor As described in the High Efficiency Switching PowerPath Controller section, the resistor on the CLPROG pin determines the average input current limit when the switching regulator is set to either the 1x mode (USB 100mA), the 5x mode (USB 500mA) or the 10x mode. The input current will be comprised of two components, the current that is used to drive VOUT and the quiescent current of the switching regulator. To ensure that the USB specification is strictly met, both components of input current should be considered. The Electrical Characteristics table gives values for quiescent currents in either setting as well as current limit programming accuracy. To get as close to the 500mA or 100mA specifications as possible, a 1% resistor should be used. Recall that IVBUS = IVBUSQ + VCLPROG/RCLPPROG * (hCLPROG +1). An averaging capacitor or an R-C combination is required in parallel with the CLPROG resistor so that the switching regulator can determine the average input current. This network also provides the dominant pole for the feedback loop when current limit is reached. To ensure stability, the capacitor on CLPROG should be 0.47F or larger. Alternatively, faster transient response may be achieved with 0.1F in series with 8.2. Choosing the PowerPath Inductor Because the input voltage range and output voltage range of the power path switching regulator are both fairly narrow, the LTC3556 was designed for a specific inductance value of 3.3H. Some inductors which may be suitable for this application are listed in Table 6.
Table 6. Recommended Inductors for PowerPath Controller
INDUCTOR L TYPE (H) LPS4018 D53LC DB318C WE-TPC Type M1 CDRH6D12 CDRH6D38 3.3 3.3 3.3 3.3 3.3 3.3 MAX IDC (A) 2.2 MAX DCR () 0.08 SIZE IN mm (L x W x H)
MANUFACTURER
3.9 x 3.9 x 1.7 Coilcraft www.coilcraft.com
2.26 0.034 5.0 x 5.0 x 3.0 Toko 1.55 0.070 3.8 x 3.8 x 1.8 www.toko.com 1.95 0.065 4.8 x 4.8 x 1.8 Wurth Elektronik www.we-online.com 2.2 0.0625 6.7 x 6.7 x 1.5 Sumida 3.5 0.020 7.0 x 7.0 x 4.0 www.sumida.com
VBUS and VOUT Bypass Capacitors The style and value of capacitors used with the LTC3556 determine several important parameters such as regulator control-loop stability and input voltage ripple. Because the LTC3556 uses a step-down switching power supply from VBUS to VOUT , its input current waveform contains high frequency components. It is strongly recommended that a low equivalent series resistance (ESR) multilayer ceramic capacitor be used to bypass VBUS. Tantalum and aluminum capacitors are not recommended because of their high ESR. The value of the capacitor on VBUS directly controls the amount of input ripple for a given load current. Increasing the size of this capacitor will reduce the input ripple.
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LTC3556 APPLICATIONS INFORMATION
To prevent large VOUT voltage steps during transient load conditions, it is also recommended that a ceramic capacitor be used to bypass VOUT. The output capacitor is used in the compensation of the switching regulator. At least 4F of actual capacitance with low ESR are required on VOUT. Additional capacitance will improve load transient performance and stability. Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight board layout and an unbroken ground plane will yield very good performance and low EMI emissions. There are several types of ceramic capacitors available, each having considerably different characteristics. For example, X7R ceramic capacitors have the best voltage and temperature stability. X5R ceramic capacitors have apparently higher packing density but poorer performance over their rated voltage and temperature ranges. Y5V ceramic capacitors have the highest packing density, but must be used with caution, because of their extreme nonlinear characteristic of capacitance vs voltage. The actual in-circuit capacitance of a ceramic capacitor should be measured with a small AC signal (ideally less than 200mV) as is expected in-circuit. Many vendors specify the capacitance vs voltage with a 1VRMS AC test signal and as a result overstate the capacitance that the capacitor will present in the application. Using similar operating conditions as the application, the user must measure or request from the vendor the actual capacitance to determine if the selected capacitor meets the minimum capacitance that the application requires. 400mA Step-Down Switching Regulator Inductor Selection Many different sizes and shapes of inductors are available from numerous manufacturers. Choosing the right inductor from such a large selection of devices can be overwhelming, but following a few basic guidelines will make the selection process much simpler. The buck converters are designed to work with inductors in the range of 2.2H to 10H. For most applications a 4.7H inductor is suggested for both buck regulators. Larger value inductors reduce ripple current which improves output ripple voltage. Lower value inductors result in higher ripple current and improved transient response time. To maximize efficiency, choose an inductor with a low DC resistance. For a 1.2V output, efficiency is reduced about 2% for 100m series resistance at 400mA load current, and about 2% for 300m series resistance at 100mA load current. Choose an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short-circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the buck converters. Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or Permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. Inductors that are very thin or have a very small volume typically have much higher core and DCR losses, and will not give the best efficiency. The choice of which style inductor to use often depends more on the price vs size, performance and any radiated EMI requirements than on what the LTC3556 requires to operate. The inductor value also has an effect on forced burst and Burst Mode operations. Lower inductor values will cause the Burst Mode and forced Burst Mode switching frequencies to increase. Table 7 shows several inductors that work well with the LTC3556's buck regulators. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors.
Table 7. Recommended Inductors for 400mA Step-Down Switching Regulators
NDUCTOR TYPE DE2818C DE2812C L MAX MAX (H) IDC (A) DCR () 4.7 4.7 1.25 1.15 0.9 1.3 0.8 1.1 0.072* 0.13* 0.11 0.162 0.246 0.2 SIZE IN mm (L x W x H) MANUFACTURER
3.0 x 2.8 x 1.8 Toko www.toko.com 3.0 x 2.8 x 1.2 4.0 x 4.0 x 1.8 Sumida www.sumida.com 3.1 x 3.1 x 1.8 Cooper www.cooperet. 3.1 x 3.1 x 1.2 com 3.0 x 3.0 x 1.5 Coilcraft www.coilcraft.com
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CDRH3D16 4.7 SD3118 SD3112 LPS3015 *Typical DCR 4.7 4.7 4.7
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LTC3556 APPLICATIONS INFORMATION
400mA Step-Down Switching Regulator Input/Output Capacitor Selection Low ESR (equivalent series resistance) MLCC capacitors should be used at both buck regulator outputs as well as at each buck regulator input supply (VIN1 and VIN2). Only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 10F output capacitor is sufficient for most applications. For good transient response and stability the output capacitor should retain at least 4F of capacitance over operating temperature and bias voltage. Each buck regulator input supply should be bypassed with a 1F capacitor. Consult with capacitor manufacturers for detailed information on their selection and specifications of ceramic capacitors. Many manufacturers now offer very thin (<1mm tall) ceramic capacitors ideal for use in height-restricted designs. Table 8 shows a list of several ceramic capacitor manufacturers.
Table 8. Recommended Ceramic Capacitor Manufacturers
AVX Murata Taiyo Yuden Vishay Siliconix TDK www.avxcorp.com www.murata.com www.t-yuden.com www.vishay.com www.tdk.com
Table 9. Recommended Inductors for Buck-Boost Regulator
INDUCTOR L TYPE (H) LPS4018 D53LC 7440430022 CDRH4D22/ HP SD14 3.3 2.2 2.0 2.2 2.2 2.0 MAX IDC (A) 2.2 2.5 3.25 2.5 2.4 MAX DCR () 0.08 0.07 0.02 SIZE IN mm (L x W x H)
MANUFACTURER
3.9 x 3.9 x 1.7 Coilcraft 3.9 x 3.9 x 1.7 www.coilcraft.com 5.0 x 5.0 x 3.0 Toko www.toko.com
0.028 4.8 x 4.8 x 2.8 Wurth-Elektronik www.we-online.com 0.044 4.7 x 4.7 x 2.4 Sumida www.sumida.com 5.2 x 5.2 x 1.45 Cooper www.cooperet.com
2.56 0.045
Buck-Boost Regulator Input/Output Capacitor Selection Low ESR MLCC capacitors should also be used at both the buck-boost regulator output (VOUT3) and the buck-boost regulator input supply (VIN3). Again, only X5R or X7R ceramic capacitors should be used because they retain their capacitance over wider voltage and temperature ranges than other ceramic types. A 22F output capacitor is sufficient for most applications. The buck-boost regulator input supply should be bypassed with a 2.2F capacitor. Refer to Table 8 for recommended ceramic capacitor manufacturers. Buck-Boost Regulator Output Voltage Programming The buck-boost regulator can be programmed for output voltages greater than 2.75V and less than 5.5V. The fullscale output voltage is programmed using a resistor divider from the VOUT3 pin connected to the FB3 pin such that: R1 +1 VOUT 3 = VFB3 R2 where VFB3 ranges from 0.425V to 0.8V.
Buck-Boost Regulator Inductor Selection Inductor selection criteria for the buck-boost are similar to those given for the 400mA step-down switching regulators. The buck-boost converter is designed to work with inductors in the range of 1H to 5H. For most applications a 2.2H inductor will suffice. Choose an inductor with a DC current rating at least 2 times larger than the maximum load current to ensure that the inductor does not saturate during normal operation. If output short circuit is a possible condition, the inductor should be rated to handle the maximum peak current specified for the buck-boost converter. Table 9 shows several inductors that work well with the LTC3556's buck-boost regulator. These inductors offer a good compromise in current rating, DCR and physical size. Consult each manufacturer for detailed information on their entire selection of inductors.
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LTC3556 APPLICATIONS INFORMATION
Closing the Feedback Loop The LTC3556 incorporates voltage mode PWM control. The control to output gain varies with operation region (buck, boost, buck-boost), but is usually no greater than 20. The output filter exhibits a double-pole response given by: 1 fFILTER _ POLE = Hz 2 * * L * COUT where COUT is the output filter capacitor. The output filter zero is given by: fFILTER _ ZERO = 1 2 * * RESR * COUT Hz The unity-gain frequency of the error amplifier with the Type I compensation is given by: fUG = 1 Hz 2 * * R1 * CP1
Most applications demand an improved transient response to allow a smaller output filter capacitor. To achieve a higher bandwidth, Type III compensation is required. Two zeros are required to compensate for the double-pole response. Type III compensation also reduces any VOUT3 overshoot at start-up. The compensation network depicted in Figure 6 yields the transfer function: VC3 1 = VOUT 3 R1 (C1 + C2) * (1 + sR2C2) [1 + s (R1 + R3)C3 ] s 1 + sR2(C1|| C2) (1 + sR3C3)
where RESR is the capacitor equivalent series resistance. A troublesome feature in boost mode is the right-half plane zero (RHP), and is given by: fRHPZ = VIN2 Hz 2 * * IOUT * L * VOUT
The loop gain is typically rolled off before the RHP zero frequency. A simple Type I compensation network (as shown in Figure 5) can be incorporated to stabilize the loop but at the cost of reduced bandwidth and slower transient response. To ensure proper phase margin, the loop must cross unity-gain a decade before the LC double pole.
A Type III compensation network attempts to introduce a phase bump at a higher frequency than the LC double pole. This allows the system to cross unity gain after the LC double pole, and achieve a higher bandwidth. While attempting to cross over after the LC double pole, the system must still cross over before the boost right-half plane zero. If unity gain is not reached sufficiently before the right-half plane zero, then the -180 of phase lag from
VOUT3
+ +
ERROR AMP VOUT3 0.8V FB3 7 VC3 8 CP1 R2
3556 F05
0.8V FB3 7 VC3 8 C1 C2 R2
ERROR AMP
R1
R3 C3
R1
-
-
RFB
3556 F06
Figure 5. Error Amplifier with Type I Compensation
Figure 6. Error Amplifier with Type III Compensation
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LTC3556 APPLICATIONS INFORMATION
the LC double pole combined with the -90 of phase lag from the right-half plane zero will result in negating the phase bump of the compensator. The compensator zeros should be placed either before or only slightly after the LC double pole such that their positive phase contributions offset the -180 that occurs at the filter double pole. If they are placed at too low of a frequency, they will introduce too much gain to the system and the crossover frequency will be too high. The two high frequency poles should be placed such that the system crosses unity gain during the phase bump introduced by the zeros and before the boost right-half plane zero and such that the compensator bandwidth is less than the bandwidth of the error amp (typically 900kHz). If the gain of the compensation network is ever greater than the gain of the error amplifier, then the error amplifier no longer acts as an ideal op amp, and another pole will be introduced at the same point. Recommended Type III compensation components for a 3.3V output: R1: 324k RFB: 105k C1: 10pF R2: 15k C2: 330pF R3: 121k C3: 33pF COUT: 22F LOUT: 2.2H Over-Programming the Battery Charger The USB high power specification allows for up to 2.5W to be drawn from the USB port (5V x 500mA). The PowerPath switching regulator transforms the voltage at VBUS to just above the voltage at BAT with high efficiency, while limiting power to less than the amount programmed at CLPROG. In some cases the battery charger may be programmed (with the PROG pin) to deliver the maximum safe charging current without regard to the USB specifications. If there is insufficient current available to charge the battery at the programmed rate, the PowerPath regulator will reduce charge current until the system load on VOUT is satisfied and the VBUS current limit is satisfied. Programming the battery charger for more current than is available will not cause the average input current limit to be violated. It will merely allow the battery charger to make use of all available power to charge the battery as quickly as possible, and with minimal power dissipation within the battery charger. Alternate NTC Thermistors and Biasing The LTC3556 provides temperature qualified charging if a grounded thermistor and a bias resistor are connected to NTC. By using a bias resistor whose value is equal to the room temperature resistance of the thermistor (R25) the upper and lower temperatures are pre-programmed to approximately 40C and 0C, respectively (assuming a Vishay "Curve 1" thermistor). The upper and lower temperature thresholds can be adjusted by either a modification of the bias resistor value or by adding a second adjustment resistor to the circuit. If only the bias resistor is adjusted, then either the upper or the lower threshold can be modified but not both. The other trip point will be determined by the characteristics of the thermistor. Using the bias resistor in addition to an adjustment resistor, both the upper and the lower temperature trip points can be independently programmed with the constraint that the difference between the upper and lower temperature thresholds cannot decrease. Examples of each technique follow. NTC thermistors have temperature characteristics which are indicated on resistance-temperature conversion tables. The Vishay-Dale thermistor NTHS0603N011-N1003F used ,
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29
LTC3556 APPLICATIONS INFORMATION
in the following examples, has a nominal value of 100k and follows the Vishay "Curve 1" resistance-temperature characteristic. In the explanation below, the following notation is used. R25 = Value of the thermistor at 25C RNTC|COLD = Value of thermistor at the cold trip point RNTC|HOT = Value of thermistor at the hot trip point rCOLD = Ratio of RNTC|COLD to R25 rHOT = Ratio of RNTC|COLD to R25 RNOM = Primary thermistor bias resistor (see Figure 7a) R1 = Optional temperature range adjustment resistor (see Figure 7b) The trip points for the LTC3556's temperature qualification are internally programmed at 0.349 * VBUS for the hot threshold and 0.765 * VBUS for the cold threshold. Therefore, the hot trip point is set when: RNTCHOT | RNOM + RNTCHOT | * VBUS = 0.349 * VBUS to the nonlinear behavior of the thermistor. The following equations can be used to easily calculate a new value for the bias resistor: RNOM = RNOM = rHOT * R25 0.536 rCOLD * R25 3.25
where rHOT and rCOLD are the resistance ratios at the desired hot and cold trip points. Note that these equations are linked. Therefore, only one of the two trip points can be chosen, the other is determined by the default ratios designed in the IC. Consider an example where a 60C hot trip point is desired. From the Vishay Curve 1 R-T characteristics, rHOT is 0.2488 at 60C. Using the above equation, RNOM should be set to 46.4k. With this value of RNOM, the cold trip point is about 16C. Notice that the span is now 44C rather than the previous 40C. This is due to the decrease in "temperature gain" of the thermistor as absolute temperature increases. The upper and lower temperature trip points can be independently programmed by using an additional bias resistor as shown in Figure 7b. The following formulas can be used to compute the values of RNOM and R1: RNOM = rCOLD - rHOT * R25 2.714
and the cold trip point is set when: RNTC|COLD RNOM + RNTC|COLD * VBUS = 0.765 * VBUS
Solving these equations for RNTC|COLD and RNTC|HOT results in the following: RNTC|HOT = 0.536 * RNOM and RNTC|COLD = 3.25 * RNOM By setting RNOM equal to R25, the above equations result in rHOT = 0.536 and rCOLD = 3.25. Referencing these ratios to the Vishay Resistance-Temperature Curve 1 chart gives a hot trip point of about 40C and a cold trip point of about 0C. The difference between the hot and cold trip points is approximately 40C. By using a bias resistor, RNOM, different in value from R25, the hot and cold trip points can be moved in either direction. The temperature span will change somewhat due
R1 = 0.536 * RNOM - rHOT * R25 For example, to set the trip points to 0C and 45C with a Vishay Curve 1 thermistor choose: RNOM = 3.266 - 0.4368 * 100k = 104.2k 2.714
The nearest 1% value is 105k. R1 = 0.536 * 105k - 0.4368 * 100k = 12.6k The nearest 1% value is 12.7k. The final solution is shown in Figure 7b and results in an upper trip point of 45C and a lower trip point of 0C.
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30
LTC3556 APPLICATIONS INFORMATION
VBUS
VBUS
LTC3556 NTC BLOCK
RNOM 100k NTC 3 RNTC 100k
0.765 * VBUS
-
TOO_COLD
+
T
-
TOO_HOT 0.349 * VBUS
+
+
NTC_ENABLE 0.017V * VBUS
-
3556 F07a
(7a)
VBUS
VBUS
LTC3556 NTC BLOCK
RNOM 105k NTC 3
0.765 * VBUS
-
TOO_COLD
+
R1 12.7k 0.349 * VBUS T RNTC 100k
-
TOO_HOT
+
+
NTC_ENABLE 0.017 * VBUS
-
3556 F07b
(7b)
Figure 7. NTC Circuits
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31
LTC3556 APPLICATIONS INFORMATION
USB Inrush Limiting When a USB cable is plugged into a portable product, the inductance of the cable and the high-Q ceramic input capacitor form an L-C resonant circuit. If the cable does not have adequate mutual coupling or if there is not much impedance in the cable, it is possible for the voltage at the input of the product to reach as high as twice the USB voltage (~10V) before it settles out. To prevent excessive voltage from damaging the LTC3556 during a hot insertion, it is best to have a low voltage coefficient capacitor at the VBUS pin to the LTC3556. This is achievable by selecting an MLCC capacitor that has a higher voltage rating than that required for the application. For example, a 16V, X5R, 10F capacitor in a 1206 case would be a more conservative choice than a 6.3V, X5R, 10F capacitor in a smaller 0805 case. The size of the input overshoot will be determined by the "Q" of the resonant tank circuit formed by CIN and the input lead inductance. It is recommended to measure the input ringing with the selected components to verify compliance with the Absolute Maximum specifications. Alternatively, the following soft connect circuit (Figure 8) can be employed. In this circuit, capacitor C1 holds MP1 off when the cable is first connected. Eventually C1 begins to charge up to the USB input voltage applying increasing gate support to MP1. The long time constant of R1 and C1 prevent the current from building up in the cable too fast thus dampening out any resonant overshoot. Printed Circuit Board Layout Considerations In order to be able to deliver maximum current under all conditions, it is critical that the Exposed Pad on the backside of the LTC3556 package be soldered to the PC board ground. Failure to make thermal contact between the Exposed Pad on the backside of the package and the copper board will result in higher thermal resistances. Furthermore, due to its high frequency switching circuitry, it is imperative that the input capacitors, inductors and output capacitors be as close to the LTC3556 as possible and that there be an unbroken ground plane under the LTC3556 and all of its external high frequency components. High frequency currents such as the VBUS, VIN1, VIN2 and VIN3 currents on the LTC3556, tend to find their way along the ground plane in a myriad of paths ranging from directly back to a mirror path beneath the incident path on the top of the board. If there are slits or cuts in the ground plane due to other traces on that layer, the current will be forced to go around the slits. If high frequency currents are not allowed to flow back through their natural least-area path, excessive voltage will build up and radiated emissions will occur. There should be a group of vias under the grounded backside of the package leading directly down to an internal ground plane. To minimize parasitic inductance, the ground plane should be on the second layer of the PC board.
MP1 Si2333 5V USB INPUT C1 100nF USB CABLE R1 40k C2 10F VBUS
LTC3556
GND
3556 F08
Figure 8. USB Soft Connect Circuit
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32
LTC3556 APPLICATIONS INFORMATION
The GATE pin for the external ideal diode controller has extremely limited drive current. Care must be taken to minimize leakage to adjacent PC board traces. 100nA of leakage from this pin will introduce an offset to the 15mV ideal diode of approximately 10mV. To minimize leakage, the trace can be guarded on the PC board by surrounding it with VOUT connected metal, which should generally be less that one volt higher than GATE. When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3556. 1. Are the capacitors at VBUS, VIN1, VIN2 and VIN3 as close as possible to the LTC3556? These capacitors provide the AC current to the internal power MOSFETs and their drivers. Minimizing inductance from these capacitors to the LTC3556 is a top priority. 2. Are COUT and L1 closely connected? The (-) plate of COUT returns current to the GND plane, and then back to CIN. 3. Keep sensitive components away from the SW pins. Battery Charger Stability Considerations The LTC3556's battery charger contains both a constantvoltage and a constant-current control loop. The constantvoltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, however, may add enough series inductance to require a bypass capacitor of at least 1F from BAT to GND. Furthermore, when the battery is disconnected, a 100F OSCON B6 capacitor in series with a 0 jumper from BAT to GND is required to keep ripple voltage low. High value, low ESR multilayer ceramic chip capacitors reduce the constant-voltage loop phase margin, possibly resulting in instability. Ceramic capacitors up to 22F may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2 to 1 of series resistance. In constant-current mode, the PROG pin is in the feedback loop rather than the battery voltage. Because of the additional pole created by any PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capacitance on the PROG pin, the battery charger is stable with program resistor values as high as 25k. However, additional capacitance on this node reduces the maximum allowed program resistor. The pole frequency at the PROG pin should be kept above 100kHz. Therefore, if the PROG pin has a parasitic capacitance, CPROG, the following equation should be used to calculate the maximum resistance value for RPROG: RPROG 1 2 * 100kHz * CPROG
3556 F09
Figure 9. Higher Frequency Ground Currents Follow Their Incident Path. Slices in the Ground Plane Cause High Voltage and Increased Emissions
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33
LTC3556 TYPICAL APPLICATION
Watchdog Microcontroller Operation
L1 3.3H
USB/WALL 4.5V TO 5.5V
25 C1 10F 100k 3 20 T 2k 8.25 0.1F 2 3.01k
VBUS NTC PROG CLPROG
SW VOUT GATE BAT GND CHRG VOUT3
26 24 22 23
TO OTHER LOADS MP1 C2 22F RED 2.5V TO 3.3V 1A 510
+
29 21 12 10pF
Li-Ion
HDD
121k 330pF 324k 22F 105k L2 2.2H 2.2F 33pF
1 1F 10
LDO3V3 DVCC
7 FB3 14 SWCD3 9 11 L3 4.7H 1.02M
VC3
8
15k
SWAB3 PUSHBUTTON MICROCONTROLLER VIN3 LTC3555 SW2
19
1.8V 400mA
I/O
2
13,16
FB2 I
2C (SCL, SDA)
17 806k 18 L4 4.7H 806k
10pF 10F 1F MICROPROCESSOR 0.8V TO 1.6V 400mA CORE POR 10pF 806k 10F 1F 10k
C1: MURATA GRM21BR61A106KE19 C2: TDK C2012X5R0J226M L1: COILCRAFT LPS4018-332LM L2: COILCRAFT LPS4018-222MLC L3, L4: TOKO 1098AS-4R7M MP1: SILICONIX Si2333 28 27 ENALL SEQ
VIN2 SW1
4
FB1
6
VIN1 PGOODALL
5 15
3556 TA02
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34
LTC3556 PACKAGE DESCRIPTION
UFD Package 28-Lead Plastic QFN (4mm x 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
0.70 0.05
4.50 0.05 3.10 0.05 2.50 REF 2.65 0.05 3.65 0.05
PACKAGE OUTLINE
0.25 0.05 0.50 BSC 3.50 REF 4.10 0.05 5.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 0.75 0.05 R = 0.05 TYP
2.50 REF R = 0.115 TYP 27 28
PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER
0.40 0.10 1 2
5.00 0.10 (2 SIDES)
3.50 REF 3.65 0.10 2.65 0.10
(UFD28) QFN 0506 REV B
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC3556 TYPICAL APPLICATION
Pushbutton Start with Automatic Sequencing, Reverse Input Voltage Protection and 10 Second Push and Hold Hard Shutdown
USB CONNECTOR MP1 25 10F VOUT3 VC3 12 8 MEMORY VBUS
10 0.1F 1 4.7k 1k 1F
7 FB3 14 SWCD3 DVCC 9 SWAB3 15 PGOODALL LDO3V3 SW1 LTC3556 CORE 4 6 FB1
1M MN1
28 27
ENALL SEQ I2C (SCL, SDA) 13,16 19 17 SEND I2C CODE: "0x12FF1C" ONCE POWER IS DETECTED
3556 TA03
2
SDA SCL I/O
10F 10k
10F SW2 29 GND FB2
MN1: 2N7002 MP1: SILICONIX Si2333DS
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LTC4085 LTC4088/ LTC4088-1
Hot Swap is a trademark of Linear Technology Corporation.
36 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0208 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2008

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